The present invention relates to an electronic device and to, for example, a technique for an electronic device including a power transistor.
A semiconductor device including a power transistor is described in, e.g., each of Patent Documents 1 and 2. Patent Document 1 discloses a structure in which the respective main surfaces of stacked semiconductor chips facing each other are electrically coupled to a common metal wiring layer and, in a region where the upper and lower semiconductor chips do not two-dimensionally overlap, a metal wiring layer is provided which is electrically coupled to the control electrodes of the semiconductor chips to lead out the control electrodes. Patent Document 2 discloses a structure in which a high-side device and a low-side device are stacked via a common conductive interface and electrically, mechanically, and thermally connected to each other.